Cache designs for energy efficiency
نویسندگان
چکیده
Cuches usually consume a significant amount of energy in modern microprocessors (e.g. superpipelined or superscalar processors). In this paper; we examine contemporary cuche design techniques and provide an analytical model for estimating cache energy consumption. We also present several novel techniques for designing an energy efjiciency cache, which include block buffering, cache subbanking, and Gray code addressing. The experimental results suggest that both block buffering and Gray code addressing techniques are ideal for instruction cache designs which tend to be accessed in consecutive sequence. Cache sub-bunking is ideal ,for both instruction and data caches. Overall, these techniques can achieve an order qf magnitude energy reduction on cuches.
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